1. Field of the Invention
The present invention generally relates to protection circuitry and more particularly to a method and structure that includes a local charge-eliminating element between the source/drain and gate of SOI transistors which may develop a voltage differential between the source/drain and gate during wafer fabrication. The proximate element eliminates the potential for charging damage from energetic processing steps.
2. Description of Related Art
One problem that exists when designing integrated circuits with silicon-over-insulator (SOI) transistors relates to the detection of which SOI transistors may be susceptible to charging damage, and to providing protection once such a susceptible device is identified. In SOI it is not possible to “tie down” a floating gate in the traditional sense, such as by adding a diode connection to the substrate or nwell. SOI technologies are inherently less susceptible to charging damage because both the source/drain and the gate tend to have similar antennae, so the potential of both nodes varies together. This is not, however, certain in all cases. The introduction of a charge-eliminating device or compensating antennas has been shown to reduce the propensity for damage; however this approach is not always sufficient. If the connection between the source/drain and the gate nodes is too remote from the susceptible transistor, and the antennas connected to the source/drain and the gate of the transistor are too large, even a metallic shorting element may be not be of sufficiently low impedance to protect the transistor against damage.